Capacitors are important components of integrated circuits. A typical capacitor formed on a semiconductor substrate includes first and second conductive layers/elements separated by a thin dielectric film. In many circuits, a capacitor is formed by forming banks of different capacitors which are then combined to form larger capacitors which match each other, e.g., two larger capacitors that each include banks of smaller capacitors. The combination of banks of smaller capacitors is intended to average out systemic variations across the entire semiconductor structure.
For example, if photolithographic processes are used to fabricate the wafer by forming patterns in the wafer layers, the photoresist is selectively exposed to light through an optical mask bearing the desired pattern. The exposed photoresist can then be selectively removed in order to generate a pattern in the substrate having features that, in the ideal case, exactly duplicate those of the optical mask. Subsequent etch or deposition of the substrate can then be performed in those areas where the photo-resist has been removed. However, processing errors are encountered during one or more of the steps in the fabrication of the wafer. For example, contaminations during the fabrication of photomasks, embedded impurities in substrates, resists, or other involved materials, may give rise to defects in the pattern(s) after the patterning process. In addition, the mask may have inherent defects which result in inconsistencies in the resulting pattern(s) created on the wafer.
One conventional technique for forming capacitors is to use interdigital, or interdigitated capacitive plates or “fingers.” The interdigitated fingers permit large scale integration of numerous capacitors on a common semiconductor substrate. However, inherent lens and/or center edge bias may introduce mismatches between larger capacitor pairs. For example, dimensional variations may occur across the surface of the wafer which lead to variations in the capacitance of individual capacitors formed on the substrate, e.g., inconsistencies with respect to the length, width, and thickness of the substrate. Accordingly, the capacitance of a capacitor formed at a first location on the substrate may deviate substantially from the capacitance of a second capacitor formed at a second location on the substrate.
Referring to FIG. 1, an interdigitated capacitor arrangement 100 on a semiconductor substrate can effectively utilize available space on the substrate. The capacitor arrangement 100 includes a first conductive structure and a second conductive structure. The first conductive structure includes an interconnect region 110 which extends laterally with respect to the semiconductor substrate, e.g., from left to right in FIG. 1 and lengthwise with respect to the substrate on which the structure is formed. The first conductive structure also includes a plurality of conductive fingers 115a-b which extend generally perpendicular to and away from the interconnect region 110, e.g., vertically in FIG. 1.
The second conductive structure includes an interconnect 120 and a plurality of conductive fingers 125a-c. As seen in FIG. 1, the fingers 125a-c also extend perpendicular to, and away from, the respective interconnect 120. In addition, the fingers 125a-c are interdigitated with the fingers 115a-b to form a capacitor array between the first and second conductive structures. An insulating material 130 acts as a dielectric between the capacitors formed by each pair of parallel, but opposite fingers 125a, 115a, etc, on the substrate.
The relatively long conductors or “fingers” 115a-b, 125a-c may provide coupling between input and output ports, or transistors (not shown, but which may be connected with the interconnects), across gaps (GF, GE) formed between the respective fingers 115a-b, 125a-c. Conventionally, the gaps (GF) between the fingers 115a-b, 125a-c and at the end of the fingers (GE) are the same. The length (L) and width (W) of the fingers will affect the capacitance of the capacitor array, e.g., by increasing or decreasing the effective area of the capacitor plates, e.g., fingers. In addition, since the conductors are mounted on a substrate, the characteristics of the substrate will also affect capacitance. For example, the variations of the dielectric constant (∈r) of the insulating material will impact the electrical characteristics. In addition, the thickness of the conductors, e.g., “W” in FIG. 1 and the resistivity (ρ) of the conductive material deposited on the substrate will also impact the electrical characteristics.
Accordingly, the capacitance of the interdigitated capacitor arrangement 100 may be varied in numerous ways. In general, an increase in capacitance is obtained by increasing the resulting area of the capacitor plates/fingers, e.g., increasing the length L of the conductors, and/or the depth of the conductors. Increasing the number of fingers and length of fingers increase the width and length, respectively, of the capacitor and required substrate. The design objectives are generally to provide the desired capacitance at the design frequency in a reasonable area. With respect to the gaps GE, GF, the capacitance generally increases as the gaps are decreased, but a minimum gap is conventionally limited by the smallest, repeatable gap achievable during fabrication. Reducing the width of the fingers in general reduces the required area, increases the characteristic impedance of the line, and lowers the effective capacitance.
Referring to FIG. 2, a conventional arrangement is illustrated that is used to address process variations and to produce matching capacitors. Banks of capacitors from different layout locations are connected to average out systemic variations occurring with respect to the span of the wafer, e.g., along the length of the substrate L as depicted in FIG. 2. Two capacitors are formed. A first capacitor is formed from capacitor 1A (Cap 1A) and capacitor 1B (Cap 1B). A second capacitor is formed from capacitor 2A (Cap 2A) and capacitor 2B (Cap 2B). Capacitors 1A and 1B, and capacitors 2A and 2B are located in adjacent corners of the area allocated for the capacitor banks and interconnected (e.g., cross connected) to average out system variations occurring with respect to the span L of the wafer. Individual capacitors 1A, 1B, 2A, and 2B may each include a capacitor array, such as that shown in FIG. 1. Further, the span L can be 100's of micron's long, which is large enough to see systemic lens and within die variations, which are not compensated by the simple cross connection of the capacitors (1A, 1B, 2A and 2B). Accordingly, the first and second capacitors may still not be accurately matched.